Voltage regulators are utilized in a variety of electrical and electro-mechanical applications. DC voltage regulators, for example, are typically implemented in the context of a static circuit that accepts a variable DC voltage input and produces a regulated DC voltage output. The output voltage is maintained for changes in input voltage and output load current. One type of voltage regulator utilized widely in industrial and commercial applications is the low dropout regulator. The “Low Dropout Regulator” also known as an LDO generally functions with a lower voltage across it before it stops regulating.
FIG. 1 illustrates a schematic diagram or a prior art electrical circuit 10 that functions as a low drop regulator. In general, circuit 10 includes a transistor 14 connected to a supply voltage 12 and a transistor 16. A transistor 18 is generally connected to transistor 16 and also to a current source 20, which is connected to ground and also connected to an output of transistor 14. A transistor 26 is also connected to transistor 14 and to a transistor 24, which in turn is connected to a capacitor 22 disposed between nodes A and B.
Transistor 24 is generally disposed between nodes A and D. A resistor 28 is connected to node D and a node G. A resistor 38 is in turn connected to node G and ground. Transistor 26 is also connected to node G. A resistor 32 is also provided, which is connected to a resistor 30. Note that resistors 30 and 32 are configured in parallel with a capacitor 34 and a resistor 36. A node C is connected to one end of resistor 30 and one end of capacitor 34 and resistor 36. An output voltage 37 can be obtained from node C, which also happens to be connected to transistor 16. One of the problems with prior art circuit 10 is that circuit 10 often requires the use of the external capacitor 34 and is unable to operate at higher supply voltages due to electrical breakdown considerations of capacitor 22. Additionally, circuit 10 requires a large circuit area.
FIG. 2 illustrates a graph 40 depicting data generated from a prior art low drop regulator such as the one depicted in FIG. 1. Graph 40 is provided in the form of a low dropout regulator bode plot in order to demonstrate marginal stability with only 33 degrees of phase margin. An area 42 in graph 40 indicates 33 degrees of stability with little margin thereof. Lines 44 and 46 plotted in graph 40 generally represent loop gain phase shift and magnitude. Graph 40 thus indicates that more than a 180 degree shift with a gain above 0 db is unstable.
One of the primary problems associated with the configuration depicted in FIGS. 1-2 is that circuit 10 does not permit capacitor 22 to withstand a voltage that is a function of Vcc or the supply voltage 12. That is, due to the design of circuit 10, capacitor 22 cannot provide optimal compensation. It is therefore believed that an improved low dropout voltage regulator design and implementation is required to overcome the inherent problems associated with the prior art, such as, for example, circuit 10.